An approximated soft error analysis technique for gate-level designs

As the semi-conductor technology advances, the evaluation of soft error hardness for modern electrical and electronic devices becomes more generalized. Related studies have mainly focused on the soft error rate analysis of both combinational and sequential logic circuits, which includes techniques for dynamic simulation, and pathbased statistical estimation. In particular, non-dynamic approaches make the entire framework simple and compact. However, when the design under test has a large number of propagation paths, there is still a problem of increasing time complexity. This paper introduces an approximated soft error analysis technique, which constructs lookup tables with which to estimate transient pulses at the primary outputs. The whole process can be finished in polynomial time complexity. We employ node conditional probability to calculate the logical propagation probabilities without using static probability. The experimental results show that compared to the full-path analysis, the approximated technique can speed up the analysis time by 300% while the corresponding error rates for the evaluation results that are obtained are within 16% difference.